1. Field of the invention
The present invention relates to an ECL-TTL level converting circuit, and more specifically to an ECL-TTL level converting circuit capable of preventing an increase of a low level potential due to parasitic resistance components of a package and the like.
2. Description of Related Art
Hitherto, so-called ECL-TTL level converting circuits have been widely used in conventional logic circuits for the purpose of interfacing between an ECL (emitter coupled logic) circuit and a TTL (transistor transistor logic) circuit. However, most of the conventional ECL-TTL circuits have such a circuit construction that when a low level signal of a TTL level is outputted, a maximum current is flowed into a ground. Therefore, a ground level will be increased by parasitic resistance components of a package and a ground line wiring of a voltage supply, with the result that a potential of the low level output signal will be adversely increased.